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description gm3255 products are 280 khz switching regulators with a high efficiency, 1.5 a integrated switch. these parts oper- ate over a wide input voltage range, from 2.7 v to 30 v. the flexibility of the design allows the chips to operate in most power supply configurations, including boost, flyback, forward, inverting, and sepic. the ics utilize current mode architecture, which allows excellent load and line reg- ulation, as well as a practical means for limiting current. combining high frequency operation with a highly inte- grated regulator circuit results in an extremely compact power supply solution. the circuit design includes provi- sions for features such as frequency synchronization, shut- down, and feedback controls for either positive or negative voltage regulation. application boost regulators ccfl backlight driver laptop computer supplies multiple output flyback supplies inverting supplies tft lcd bias supplies typical applica tion circuits features integrated power switch: 1.5 a guaranteed input voltage range: 2.7 v to 30 v high frequency allows for small components minimum external components easy external synchronization built in overcurrent protection frequency foldback reduces component stress during an overcurrent condition thermal shutdown with hysteresis regulates either positive or negative output voltages shut down current: 50 a maximum wide temperature range commercial commercial grade : 0 to 70c (gm3255) gm3255 v c fb test ss v sw pgnd agnd v cc 1 2 3 4 5 6 7 8 r2 3.72k c1 0.01f ss 3.3v r1 5k r3 1.28k c2 22f l1 22h d1 mbrs120t3 v out 5v c3 22f + + www.gammamicro.com g m 3 2 5 5 v 0 . 1 1 1
marking information & pin configura tions (top view) sop-8 & nsop-8 1 2 3 4 8 7 6 5 v c fb ss test agnd v cc pgnd v sw gm3255 ayww a = assembly location y = y ear w w = work week ordering number package shipping gm3255s8t GM3255NS8T gm3255s8r gm3255ns8r sop - 8 nsop - 8 sop - 8 nsop - 8 100 units / tube 100 units / tube 2,500 units / t ape & reel 2,500 units / t ape & reel pin description pin number pin symbol function 1 2 3 4 5 6 7 8 v c fb test ss v cc agnd pgnd v sw loop compensation pin. the v pin is the output of the error amplifier and is used for c loop compensation, current limit and start. loop compensation can be implemented by a simple rc network as shown in the application diagram on page 2 as r1 and c1. positive regulator feedback pin. this pin senses a positive output voltage and is referenced to 1.276v. when the voltage at this pin falls below 0.4 v , chip switching frequency reduces to 20% of the nominal frequency. these pins are connected to internal test logic and should either be left floating or tied to ground. connection to a voltage between 9.5v and 15v shuts down the internal oscillator and leaves the power switch running. synchronization and shutdown pin. this pin may be used to synchronize the part to nearly twice the base frequency. a ttl low shut the part down and put it into low current mode. if synchronization is not used, this pin should be either tied high or left floating for normal operation. input power supply pin. this pin supplies power to the part and should have a bypass capacitor connected to agnd. analog ground. this pin provides a clean ground for the controller circuitry ans should not be in the path of large currents. the output voltage sensing resistors should be connected to the ic substrate. power ground. this pin is the ground connection for the emitter of the power switching transistor. connection to a good ground plane is essential. high current switch pin. this pin connects internally to the collector of the power switch. the open voltage across the power switch can be as high as 40v. t o minimize radiation, use a trace as short as practical. absolute maximum ratings parameter value units package thermal resistance junction-to-case, r q jc junction-to-ambient, r q jc junction temperature range, t j storage temperature range, t stg esd, human body model 45 165 -40 to +150 -65 to +150 230 1.2 c / w c / w kv c c c lead temperature (peak) (reflow - soldering 60 maximum above 183c) s e c. g m 3 2 5 5 2 * for detail ordering number identification, please see last page. * the maximum package power dissipation must be observed.
block diagram v cc ss fb ag nd v sw pg nd sh utd ow n de lay ti me r 2.0 v re gul ato r th erm al sh utd ow n sy nc os cill ato r fre que ncy sh ift 5 :1 pw m lat ch s q dri ver 0.4 v de tec tor 1.2 76 v po siti ve err or am p - + slo pe co mp en sat ion pw m co mp ara tor + - v c sw itch 63 m w ra mp su mm er x 5 r maximum ratings: pin name ic power input shutdown / sync loop compensation voltage feedback input t est pin power ground analog ground switch input pin symbol v cc ss v c fb test pgnd agnd v sw v max 30 v 30 v 6 v 10 v 6 v 0.3 v 0 v 40 v v min -0.3 v -0.3 v -0.3 v -0.3 v -0.3 v -0.3 v 0 v -0.3 v i source n / a 1 ma 10 ma 1 ma 1 ma 4 a n / a 10 ma i sink 200 ma 1 ma 10 ma 1 ma 1.0 ma 10 ma 10 ma 3 a test g m 3 2 5 5 3 4a
electrical characteristics (2.7 v < v < 30 v; industrial grade: 0c < t < 70c; commercial grade: 0c < t < 125c; unless otherwise noted) cc j j characteristics test conditions min typ max unit fb reference voltage fb input current fb reference voltage line regulation error amp transconductance error amp gain error amp gain negative v source current c v sink current c v high clamp voltage c v low clamp voltage c base operating frequency reduced operating frequency maximum duty cycle fb frequency shift threshold sync range sync pulse transition threshold ss bias current shutdown threshold shutdown delay error amplifier section oscillator section sync/ shutdown section sync range shutdown threshold v tied to fb; measure at fb c fb = v ref v = fb c i = 25 a vc (note 2) (note 2) fb = 1.0v, v =1.25v c fb = 1.5v, v = 1.25v c fb = 1.0v; v sources 25a c fb = 1.5v, v sinks 25a c reduce v from 1.5v until switching c stops fb = 1.0v fb = 0v - frequency drops to reduced operating frequency rise time = 20ns ss = 0v ss = 3.0v - 2.7 v v 12v cc 12 v < v 30v cc 1.246 -1.0 - 300 200 100 25 200 1.5 0.25 0.75 230 30 90 0.36 320 2.5 -15 - 0.5 12 12 1.276 0.1 0.01 550 500 180 50 625 1.7 0.50 1.05 280 52 94 0.40 - - -3.0 3.0 0.85 80 36 v a % / v mho v / v v / v a a v v v khz khz % v khz v a s 1.300 1.0 0.03 800 - 320 90 1500 1.9 0.65 1.30 310 120 - 0.44 500 - - 8.0 350 200 1.2 v threshold c (note 1) the maximum package power dissipation must be observed. (note 2) guaranteed by design, not 100% tested in production. - g m 3 2 5 5 4 s power management
electrical characteristics (2.7 v < v < 30 v; industrial grade: 0c < t < 70c; commercial grade: 0c < t < 125c; unless otherwise noted) cc j j test conditions min typ max unit characteristics test conditions min power switch section switch saturation voltage switch current limit minimum pulse width switch leakage general section operating current shutdown mode current minimum operation input voltage thermal shutdown thermal hysteresis d i / d v cc sw i = 1.5a, (note 2) switch i = 1.0a, 0c t 85c switch j i =1.0a, -40c t 0c(note 2) switch a i = 10ma switch 50% duty cycle(note 2) 80% duty cycle(note 2) fb = 0 v, i =4.0a(note 2 ) sw 2.7 v v 12v, 10ma i 1.0a cc sw 12v v 30v, 10ma i 1.0a cc sw 2.7 v v 12v, 10ma i 1.5a cc sw (note 2) 12v v 30v, 10ma i 1.5a cc sw (note 2) v = 40 v, v = 0v sw cc i= 0 sw v < 0.8v, ss = 0v , 2.7v v 12v cc c v < 0.8v, ss = 0v , 12v v 30v cc c v switching, maximum i = 10ma sw sw (note2) (note2) - 1.6 1.5 200 150 - - - - - - - - - - - - - 0.8 0.55 0.75 0.09 1.9 1.7 250 10 - 17 - 2.0 5.5 12 - 2.45 180 25 1.4 1.00 1.30 0.45 2.4 2.2 300 30 100 30 100 100 8.0 60 100 2.70 210 - v a ns ma / a a ma a v c c (note 2) guaranteed by design, not 100% tested in production. g m 3 2 5 5 5
typical performance characteristics 0 50 100 temperature (c) figure 2. minimum input voltage vs. temperature 1.9 1.8 1.7 1.6 1.5 v ( v ) in figure 3. switching frequency vs. temperature (gm3255 only) 285 280 275 270 265 260 255 0 50 100 temperature (c) f o s c ( k h z ) figure 4. current limit vs. temperature 2.60 2.50 2.40 2.30 2.20 0 50 100 temperature (c) c u r r e n t ( a ) v = 30 v cc v = 12v cc v = 2.7v cc 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 c u r r e n t ( m a ) figure 1. i (no switching) vs. cc temperature v = 30 v cc v = 12v cc v = 2.7v cc 0 50 100 temperature (c) figure 5. maximum duty cycle vs. temperature 99 98 97 96 95 94 93 0 50 100 temperature (c) d u t y c y c l e ( % ) v = 30v cc v = 12v cc v = 22.7v cc g m 3 2 5 5 6
application informa tion current mode control gm3255 family incorporates a current mode control scheme. in which the pwm ramp signal is derived from the power switch current. this ramp signal is compared to the output of the error amplifier to control the on-time power switch. the oscillator is used as a fixed- frequency clock to ensure a constant operational fre- quency. the resulting control scheme features several advantages over conventional voltage mode control. first, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. this eliminates the delay caused by the output filter and er- ror amplifier, which is commonly found in voltage mode controllers. the second benefit comes from inherent pulse-by pulse current limiting by merely clamping the peak switching current. finally, current mode com- mands an output current rather than voltage, then the filter offers only a single pole to the feedback loop. this allows both a simpler compensation and a higher gain- bandwidth over a comparable voltage mode circuit. without discrediting its apparent merits, current mode control comes with its own peculiar problems, and mainly subharmonic oscillation at duty cycles over 50%. the gm3255 family solves this problem by adopting a slope compensation scheme, in which, a fixed ramp generated by the oscillator is added to the current ramp. a proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. oscillator and shutdown shown in figure 6. the power switch is turned off by the output of the pwm comparator. a ttl-compatible sync input at the ss pin is capa- ble of syncing up to 1.8 times the base oscillator fre- quency. as shown in figure 7, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator goes high, thereby resetting the oscillator. the sync oper- ation allows multiple power supplies to operate at the same frequency. a sustained logic low at the ss pin will shut down the ic and reduce the supply current. an additional feature includes frequency shift to 20% of the nominal frequency when either the nfb or fb pins trigger the threshold. during power up, overload, or short circuit conditions, the minimum switch on-time is limited by the pwm comparator minimum pulse width. extra switch off-time reduces the minimum duty cycle to protect external compo- nents and the ic itself. as previously mentioned, this block also produces a ramp for the slope compensation to improve regula- tor stability. error amplifier the fb pin is directly connected to the inverting in- put of the positive error amplifier, whose non- incerting input is fed by the 1.276v reference. the amplifier is transconductance amplifier with a high output impedance of approximately 1m w , as shown in figure 8. the v pin is connected to the output of c the error amplifiers and is internally clamped be- tween 0.5v and 1.7v . a typical connection at the v pin includes a capacitor in series with a resistor c to ground, forming a pole / zero for loop compensa- tion. an external shunt can be connected between the v c pin and ground to reduce its clamp voltage. current ramp v sw sync s q r v cc l d1 v c c o r loa d driv er 63 m osc illat or pw m com par ator sum me r slo pe c omp ens atio n in o ut pow er s witc h v sw x5 - + figure 6. current mode control scheme figure 8. error amplifier equivalent circuit + - cm3255 1m w positive error-amp 1.276 v fb v c c1 r1 5 k w 0.01f voltage clamp 120pf g m 3 2 5 5 7
consequently, the current limit of the internal power transistor current is reduced from its nominal value. switch driver and power switch the switch driver receives a control signal from the logic section to drive the output power switch. the switch is grounded through emitter resistors (63m w to- tal) to the pgnd pin. pgnd is not connected to the ic substrate so that switching noise can be isolated from the analog ground. the peak switching current is clamped by an internal circuit. the clamp current is guaranteed to be greater than 1.5a and varies with duty cycle due to slope compensation. the power switch can withstand a maximum voltage of 40v on the collector(v pin). the saturation voltage of the sw switch is typically less than 1v to minimize power dis- sipation. short circuit condition when a short circuit condition happens in a boost circuit, the inductor current will increase during the whole switching cycle, causing excessive current to be drawn from the input power supply. since control ics don's have the means to limit load current, an ex- ternal current limit circuit(such as a fuse or relay) has to be implemented to protect the load, power supply and ics. in other topologies, the frequency shift built into the ic prevents damage to the chip and external compo- nents. this feature reduces the minimum duty cycle and allows the transformer secondary to absorb ex- cess energy before the switch turns back on. gm3255 can be activated by either connecting the v pin to a voltage source or by enabling the ss pin. cc when the v voltage is below the minimum supply cc voltage, the v pin is in high impedance. therefore, sw current conduces directly from the input power source to the output through the inductor and diode. once v reaches approximately 1.5v, the internal power cc switch briefly turns on. this is a part of gm3255's nor- mal operation. the turn-on of the power switch ac- counts for the initial current swing. when the v pin voltage rises above the threshold, c the internal power switch starts to switch and a volt- age pulse can be seen at the v pin. detecting a sw low output voltage at the fb pin, the built-in fre- quency shift feature reduces the switching frequency to a fraction of its nominal value, reducing the mini- mum duty cycle, which is otherwise limited by the min- imum on-time of the switch. the peak current during this phase is clamped by the internal current limit. when the fb pin voltage rises above 0.4v, the fre- quency increases to its nominal value, and the peak current begins to decrease as the output ap- proaches the regulation voltage. the overshoot of the output voltage is prevented by the active pull-on, by which the sink current of the error amplifier is in- creased once an overvoltage condition is detected. the overvoltage condition is defined as when the fb pin voltage is 50mv greater than the reference volt- age. component selection frequency compensation the goal of frequency compensation is to achieve desirable transient response and dc regulation while ensuring the stability of the system. a typical compensation network, as shown in figure 9, pro- vides a frequency response of two poles and one zero. this frequency response is further illustrated in the bode plot shown in figure 9. the high dc gain in figure 10 is desirable for achieving dc accuracy over ling and load variations. the dc gain of a transconductance error amplifier can be calculated as follows: where: the low frequency pole, f , is determined by the er- p1 ror amplifier output resistance and c1 as: the first zero generated c1 and r1 is: gm3255 v c gnd r1 c1 c2 gain = g x r dc m o g = error amplifier transconductance; m r = error amplifier output resistance 1m w o figure 9. a t ypical compensation network f = z1 1 2 p c1r1 f = p1 1 2 p c1r o g m 3 2 5 5 8
when the power switch turns off, there exists a volt- age spike superimposed on top of the steady-state voltage. usually, this voltage spike is caused by transformer leakage inductance charging stray ca- pacitance between the v and pgnd pins. t o pres- sw ent the voltage at the v pin from exceeding the sw maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. another method of clamping switch volt- age is to connect a transient voltage suppressor be- tween the v pin and ground. sw magnetic component selection when choosing a magnetic component, one must consider factors such as peak current, core and fer- rite material, output voltage ripple, emi, temperature range, physical size, and cost. in boost circuits, the average inductor current is the product of output cur- rent and voltage gain (v / v ), assuming 100% out cc energy transfer efficiency. in continuous conduction mode, inductor ripple current is where: f = 280khz. the peak inductor current is equal to average cur- rent plus half of the ripple current, which should not cause inductor saturation. the above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. small ripple current provides the bene- fits of small input capacitors and greater output cur- rent capability. a core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. other core geome- tries, such as toroids, provide a closed magnetic loop to prevent emi. input capacitor selection in boost circuits, the inductor becomes part of the input filter, as shown in figure 1 1. in continuous mode, the input current waveform is triangular and does not contain a large pulsed current, during con- tinuous conduction mode, the peak to peak inductor ripple current is given in the previous section. in most applications, input capacitors in the range of 10f to 100f with an esr less than 0.3 w work well up to a full 1.5a switch current. the phase lead provided by this zero ensures that the loop has at least a 45c phase margin at the cross- over frequency. therefore, this zero should be placed close to the pole generated in the power stage, which can be identified at frequency: where: the high frequency pole, f , can be placed at the out- p2 put filter's esr zero or at half the switching frequency. placing the pole at this frequency will cut down on switching noise. the frequency of this pole is deter- mined by the value of c2 and r1: one simple method to ensure adequate phase margin is to design the frequency response with a - 20 db per decade slope, until unity-gain crossover. the crossover frequency should be selected at the midpoint between f and f where the phase margin is maximized. z1 p2 v voltage limit sw in the boost topology, v pin maximum voltage is set sw by the maximum output voltage plus the output diode forward voltage. the diode forward voltage is typically 0.5v for schottky diodes and 0.8v for ultrafast diodes where: where: n = transformer turns ratio, primary over secondary c = equivalent output capacitance of the error o amplifier 120pf; r = load resistance. load f = p1 1 2 p cr o load v = v + v sw(max) out(max) f v = output diode forward voltage. f in the flyback topology, peak v voltage is governed by: sw v = v + (v + v ) x n sw(max) cc(max) out f f = p2 1 2 p c1r1 g a i n ( d b ) d c g a i n frequency(log) f p1 f p2 f z1 figure 10. bode plot of the compensation network shown in figure 9. i = ripple v (v - v ) cc out cc ( f )( l )(v ) out g m 3 2 5 5 9
the situation is different in a flyback circuit. the input current is discontinuous and a significant pulse cur- rent is see by the input capacitors. therefore, there are two requirements for capacitors in a flyback regu- lator: energy storage and filtering. t o maintain a sta- ble voltage supply to the chip, a storage capacitor larger than 20f with low esr is required. t o reduce the noise generated by the inductor, insert a 1.0f ce- ramic capacitor between v and ground as close as cc possible to the chip. when the power switch is turned on, i is shunted to l ground and i discharges the output capacitor. out when the i ripple is small enough, i can be treated ll as a constant and is equal to input current i , in summing up, the output voltage peak-peak ripple can be calculated by: the equation can be expressed more conveniently in terms of v , v and i for design purposes as cc out out follows: the capacitor rms ripple current is: although the above equations apply only for boost cir- cuits, similar equations can be derived for flyback cir- cuits. + - figure 11. boost circuit effective input filter v cc c in r esr i l i in reducing the current limit in some applications, the designer may prefer a lower limit on the switch current than 1.5a. an external shunt can be connected between the v pin and ground to re- c duce its clamp voltage. consequently, the current limit of the internal power transistor current is reduced from its nominal value. the voltage on the v pin can be evaluated with the c equation where: r = 0.063 w , the value of the internal emitter resistor; e a = 5v/ v, the gain of the current sense amplifier . v since r and a cannot be changed by the end user, the only available method for limiting switch current be- low 1.5a is to clamp the v pin at a lower voltage. if c the maximum switch or inductor current is substituted into the equation above, the desired clamp voltage will result. a simple diode clamp, as shown in figure12, clamps the v voltage to a diode drop above the voltage on re- c sistor r3. unfortunately, such a simple circuit is not generally acceptable if v is loosely regulated. in v = out(ripple) + + i x esr in (i - i ) (1 - d) in out (c )(f) out id out (c )(f) out v = x out(ripple) + i( v - v ) out out cc (c )(f) out (i )(v )(esr) out out v cc 1 (c )(f) out 22 (i - i ) (1 - d) + (i ) (d) in out out v - v out cc v cc i = ripple = i out v = i r a cs w e v figure 12. current li miting usin g a diode c lamp v c d 1 v c c r 1 v in c 2 c 1 r 2 r 3 g m 3 2 5 5 10 e v
another solution to the current limiting problem is to externally measure the current through the switch us- ing a sense resistor. such a circuit is illustrated in figure 13. the switch current is limited to where: v = the base - emitter voltage drop of q1, typi- be(q1) cally 0.65v. the improved circuit does not require a require a regulated voltage to operate properly. unfortunately , a price must be paid for this convenience in the overall efficiency of the circuit. the designer should note that the input and output grounds are no longer common. also, the addition of the current sense resistor, r , results in a considerable power loss which in- sense crease with the duty cycle. resistor r2 and capacitor c3 form a low - pass filter to remove noise. subharmonic oscillation subharmonic oscillation (shm) is a problem found in current-mode control systems, where instability re- sults when duty cycle exceeds 50%. shm only occurs in switching regulators with a continuous inductor cur- rent. this instability is not harmful to the converter and usually does not affect the output voltage regula- tion. shm will increase the radiated em noise from the converter and can cause, under certain circum- stances, the inductor to emit high - frequency audile noise. shm is an easily remedied problem. the rising slope of the inductor current is supplemented with internal ?slope compensation? to prevent any duty cycle insta- bility from carrying through to the next switching cycle. in the gm3255, slope compensation is added during the entire switch on-time, typically in the amount of 180 ma/s. figure 13.c urrent lim iting using a current se nse resist or v c r sense q1 v cc r1 v in c2 c1 r2 c3 output ground pgnd agnd + - i = switch(peak ) v be(q1) r esense in some cases, shm can rear its ugly head despite the presence of the onboard slope compensation. the simple cure to this problem is more slope compensa- tion avoid the unwanted oscillation. in that case, an ex- ternal circuit, shown in figure 14, can be added to in- crease the amount of slope compensation used. this circuit requires only a few components and is "tacked on" to the compensation network. the dashed box contains the normal compensation circuitry to limit the bandwidth of the error amplifier. resistors r2 and r3 form a voltage divider off of the v pin. in normal operation v looks similar to a sw sw square wave, and is dependent on the converter topol- ogy. formulas for calculating v in the boost and flyback sw topologies are given in the section "v voltage limit." sw the voltage on v charges capacitor c3 when the sw switch is off, causing the voltage at the v pin to shift c upwards. when the switch turns on, c3 discharges through r3, producing a negative slope at the v pin. c the negative slope provides the slope compensation. the amount of slope compensation added by this cir- cuit is v sw figure 14. t echnique for incre asing slope compensation v c r1 c2 c1 r2 r3 v sw c3 d i d t = v ( ) (1 - e ) ( ) sw r3 r2 + r3 -(1 - d) rcf 33 s w f sw (1 - d ) r a ev g m 3 2 5 5 11
where: in selecting appropriate values for the slope compen- sation network, the designer is advised to choose a convenient capacitor, then select values for r2 and r3 such that the amount of slope compensation added is 100ma /s. then r2 may increased or decreased as necessary. of course, the series combination of r2 and r3 should be large enough to avoid drawing ex- cessive current from v . additionally , to ensure that sw the control loop stability is improved, the time constant formed by the additional components should be cho- sen such that finally, it is worth mentioning that the added slope compensation is a trade-off between duty cycle stability and transient response. the more slope compensation a designer adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the error amplifier. soft start through the addition of an external circuit, a soft-start function can be added to gm3255 of components. soft-start circuitry prevents the v pin from slamming c high during startup, thereby inhibiting the inductor cur- rent from rising at a high slope. this circuit, shown in figure 15, requires a minimum number of components and allows the soft-start cir- cuitry to activate any time the ss pin is used to restart the converter. d i / d t = the amou nt of s lope c ompe nsatio n add ed (a /s); v = the volta ge at the sw itch n ode w hen th e tran sistor sw is turn ed off (v); f = the switc hing f reque ncy, typic ally 2 80kh z sw (gm3 255) or 56 0khz d = th e duty cycle ; r = 0.0 63 w , the v alue o f the i ntern al em itter r esisto r; e a = 5v /v, the ga in of t he cu rrent sense ampl ifier. v rc < 33 1 - d f sw resistor r1 and capacitors c1 and c2 form the com- pensation network. at turn on, the voltage at the v c pin starts to come up, charging capacitor c3 through schottky diode d2, clamping the voltage at the v pin c such that switching begins when v reaches the v cc threshold, typically 1.05v (refer to graphs for detail over temperature). therefore, c3 slows the startup of the circuit by limit- ing the voltage on the v pin. the soft- start time in- c creases with the size of c3. diode d1 discharges c3 when ss is low. if the shut- down function is not used with this part, the cathode of d1 should be connected to v . in calculating junction temperature t o ensure safe operation of the gm3255, the de- signer must calculate the on-chip power dissipation and determine its expected junction temperature. internal thermal protection circuitry will turn the part off once the junction temperature exceeds 180c 30c. however, repeated operation at such high tempera- tures will ensure a reduced operating life. calculation of the junction temperature is an impre- cise but simple task. first, the power losses must be quantified. there are three major sources of power loss on gm3255: biasing of internal control circuitry, p bias switch driver, p driver switch saturation, p sat the internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even when the switch is turned off. the specifications section of this datasheet reveals that the typical oper- ating current i , due to this circuitry is 5.5 ma. q additional guidance can be found in the graph of op- erating current vs. temperature. this graph shows that i is strongly dependent on input voltage, v , and qi n temperature. then since the onboard switch is an npn transistor, the base drive current must be factored in as well. this current is drawn from the v pin, in addition to the in control circuitry current. the base drive current is listed in the specifications as d i/ d i or switch , cc sw transconductance. as before the designer will find ad- ditional guidance in the graphs. with that information, the designer can calculate v = v + v c f(d2) c3 figure 15. soft start v in ss test c3 d1 v cc 4 a v c c1 r1 c2 q ss test p = v i bias in q p = v i x xd driver in sw i cc d i sw g m 3 2 5 5 12
where i = the current through the switch; sw d = the duty cycle or percentage of switch on-time. i and d are dependent on the type of converter. in sw a boost convert, in a flyback converter, the switch saturation voltage, v , is the last ma- (ce)sat jor source of on-chip power loss. v is the collec- (ce)sat tor-emitter voltage of the internal npn transistor when it is driven into saturation by its base drive current. the value for v can be obtained from the specifica- (ce)sat tions or from the graphs, as "switch saturation voltage." thus, finally, the total on-chip power losses are power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. this heat is transferred to the surface of the ic package, but a thermal gradient exists due to the re- sistive properties of the package molding compound. the magnitude of the thermal gradient is expressed in manufacturers' data sheets as q , or junction-to- ambi- ja ent thermal resistance. the on-chip junction tempera- ture can be calculated if q , the air temperature near ja the surface of the ic, and the on-chip power dissipation are known. t = t + (p q ) ja d j a where: t = ic or fet junction temperature (c); j t = ambient temperature (c); a p = power dissipated by part in question(w); d q = junction-to ambient thermal resistance (c / w). ja for gm3255, q = 165c / w. once the designer ja has calculated t , the question of whether the gm3255 j can be used in an application is settled. if t exceeds j 150c, the absolute maximum allowable junction tem- perature, the gm3255 is not suitable for that applica- tion. i @ i x d x sw(avg) load 1 effic iency d @ v - v out in v out i @ x sw(avg) 1 effic iency v i out load v in d @ v out v + v out in n s n p p @ vi x d sat (ce)sat sw p = p + p + p d bias driver sat if t approaches 150c, the designer should con- j sider possible means of reducing the junction temper- ature. perhaps another converter topology could be selected to reduce the switch current. increasing the airflow across the surface of the chip might be consid- ered to reduce t . a output setting gm3255 develops a 1.276 v reference (v ) from ref the fb pin to ground. output voltage is set by con- necting the fb pin to an output resistor divider (figure 16). the fb pin bias current represents a small error and can usually be ignored for values of r2 up to 7k. the suggested value for r2 is 6.19k. circuit layout guidelines in any switching power supply, circuit layout is very important for proper operation. rapidly switching cur- rents combined with trace inductance generates volt- age transitions that can cause problems. therefore the following guidelines should be followed in the lay- out. 1. in boost circuits, high ac current circulates within the loop composed of the diode, output capacitor, and on-chip power transistor. the length of associated traces and leads should be kept as short as possible. in the flyback circuit, high ac current loops exist on both sides of the transformer. on the primary side, the loop consists of the input capacitor, transformer , and on-chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. just as in the boost cir- cuit, all traces and leads containing large ac current should be kept short. 2. separate the low current signal grounds from the power grounds. use single point grounding or ground plane construction for the best results. 3. locate the voltage feedback as near the ic as, pos- sible to keep the sensitive feedback wiring short. connect feedback resistors to the low current analog ground. g m 3 2 5 5 13 v out v ref fb pin r1 r2 v= out v (1 + ) ref r1 r2 r1 = r2 ( -1) v out 1.276 figure 16. output resistor divider
figure 18. additional application diagram, 5.0v to -12v/ 75ma inverting converter + + g m 3 2 5 5 c2 d2 c3 d1 c4 r2 1 2 3 4 5 6 7 8 22 f v out -12 v v c t est nf b ss 0.0 1f c1 v sw v cc ag nd pg nd v cc ss 5.0 v 5.0 k r1 r3 1.2 7 k 4.8 7 k mb rs 120 t3 mb rs 120 t3 l1 22 f 22 h 22 f gm3255 3.3 v in v c (1) fb (2) 0.1 f v cc (5) agnd (6) pgnd (7) v sw (8) 200 pf mbrs120t3 22 f 22 h figure 17. additional application diagram, 3.3 v input, 5.0 v/ 400ma output boost converter 10 f gnd 5.0 k 3.6 k gnd 5.0 v o 1.3 k g m 3 2 5 5 14 figure 19. additional application diagram, 2.7 to 13 v input, 12 v/ 200 ma output flyback converter gm 325 5 f f f f + + + +12 v v c (1 ) fb (2) v cc (5) ag nd (6) pg nd (7) v sw (8) mb rs 140 t3 22 47 1.0 gn d 2.0 k 10. 72 k gn d 1.2 8 k 47 47 nf 4.7 nf v cc -12 v t1 1:2 p6k e-1 5a 1n 414 8 mb rs 140 t3 +
figure 20. additional application diagram, -9.0 v to -28 v input, -5.0 v/700 ma output inverted buck converter gm3255 v c (1) fb (2) v cc (5) agnd (6) pgnd (7) v sw (8) 2.2 f 15 h gnd 300 gnd 5.0 k 0.01f 200 pf v in -5.0 v out 1.1 k 22 f low esr g m 3 2 5 5 15 f ig u re 2 2 . a d d it io n a l a p p li c a ti o n d ia g ra m , 4 .0 v i n p u t, 1 0 0 v / 1 0 m a o u tp u t b o o s t c o n v e rt e r w it h o u tp u t v o lt a g e m u lt ip li e r g m 3 2 5 5 v c fb a g n d p g n d v s w g n d g n d 0. 01 v c c 4. 0 v t es t s s 1 2 3 4 8 7 6 5 c 1 1 r 1 r 2 r 3 c 10 0. 1 c 8 c 9 c 1 c 2 c 3 c 4 c 5 c 6 c 7 50 v 50 v 50 v 50 v 50 v 50 v 50 v d 1 d 1 d 1 d 1 d 1 d 1 d 1 1n 41 48 99 .7 55 k / 0 .1 w , 1 % 1. 24 5 k / 0 .1 w , 1 % 2. 0 k 0. 1 10 10 0 v o 1n 41 48 1n 41 48 1n 41 48 1n 41 48 1n 41 48 1n 41 48 figure 21. additional application diagram, 2.7 v to 28 v input, 5.0 v output sepic converter gm3255 + + v c (1) fb (2) v cc (5) agnd (6) pgnd (7) v sw (8) 22 gnd 12.76 k gnd 5.0 k 0.01f 200 pf v cc 22 h low esr 22 f 22 22 37.24 k 5.0 v f f f 0. 1 0. 1 0. 1 0. 1 0. 1 0. 1 0. 1
g m 3 2 5 5 16 ?v ?v ou t ? ? -v -5 gm 325 5 v in v c v in 2.7 v t o 1 6v 1 3 8 5 4 6, 7 gn d nf b v sw s/s d2 p6k e-1 5a d3 1n 414 8 d1 mb rs 130 lt 3 c1 22 f c2 0.0 47 f c3 0.0 047 f r1 2k r3 2.4 9k 1% r2 2.4 9k 1% c4 47 f on of f 2 1 4 t1 3 ? ? ? ? + + figure 24. positive to negative converter with direct feedback figure 23. additional application diagram, 5.0 v input, 12 v output dual boost converter v cc v sw + + + g m 3 2 5 5 v c fb gn d gn d 0.0 1 f 200 pf 22 f 15 h 22 f 1.2 8 k 5.0 k ss t est 1 2 3 4 5 6 7 8 +5. 0 v ss c6 c1 r1 r2 r3 10. 72 k c5 22 f c3 d3 d2 l1 d1 -12 v +12 v c4 0.1 f ag nd pg nd gm 325 5 v in fb v c v in 2.7 v t o 1 3v 1 3 8 5 2 4 6, 7 gn d nf b v sw s/s p6k e-2 0a 1n 414 8 mb rs 140 t3 mb rs 140 t3 c1 22 f r2 1.21 k 1% r1 13k 1% c2 0.0 47 f c3 0.00 47 f r3 2k r5 2.4 9k 1% r4 12. 1k 1% v ou t 15v c4 47 f c5 47 f on of f 2, 3 6, 7 5 t1 4 8 8 1 ? ? ? ? ? ? + + + + -v ou t -15 v figure 25. dual output flyback converter with over voltage protetion
g m 3 2 5 5 17 v out -3 v 250ma v in 5v 8 3 1 + + r4 2k r2 4.99k 1% r1 1k 1% c4 0.047f c6 0.1 f c3 47f 16v c1 22 f 10v c2 47 f 16v c5 0.0047f 4 1 3 l1 2 d1 + 5 4 7 6 g m 3 2 5 5 v in s/s gnd gnd s v nfb v c sw figure 26. low ripple 5v to -3v "cuk" converter on off 2.7v to v in dimming d2 1n4148 q2 1n5818 d1 1n4148 562 w * 20k 10k 330 w 10 1 2 3 4 5 q1 10 f c1 0.1 f 4.5v to 30v v in v sw v fb v c gnd s/s 5 8 4 2 1 6, 7 gm3255 2 f 0.1 f l1 33 f t1 lamp c2 27pf 5ma max 2.2 f 5.5v 22k 1n4148 optional remote dimming + + + figure 27. ccfl supply v in 4 v t o 9 v 1 2 8 5 4 6, 7 gm3255 v in gnd v c fb s/s c1 33 f 20v c4 0.047f c5 0.0047f r1 2k r3 6.19k 1% r2 18.7k 1% v out 5v c3 100 f 10v on off l1a 10 h l1b 10 h c2 1 f mbrs130lt3 + + s w v figure 28. 2 li - lion cell to 5v sepic converter
g m 3 2 5 5 18 0.275 7.0 0.155 4.0 0.060 1.52 0.050 1.270 0.024 0.6 inches mm ( ) pad layout sop-8 p ackage outline dimensions 0.236 0.008 0.050 nom 1.270 nom +0.21 -0.20 5.990 3.91 0.1 +0.003 -0.004 0.154 pin indent 1.600 0.130 0.063 0.005 0.057 nom 1.450 nom 0.175 0.075 0.007 0.003 +0.004 -0.003 0.016 +0.10 -0.08 0.410 +0.0018 -0.0005 0.008 +0.05 -0.01 0.200 +0.013 -0.022 0.028 +0.33 -0.56 0.710 +0.002 -0.004 0.191 +0.05 -0.10 4.850 inches mm ( ) 0 ~ 8 nsop-8 package outline dimensions exposed pad version only 95 x 130 90 x 90
g m 3 2 5 5 19 ordering number gm 3255 s8 r gamma micro. circuit type package s8: so-8 shipping r: t ape & reel ns8: nsop-8

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